# ** Warning: (vcom-6) -- Waiting for lock by "orange@LAPTOP-K1M68Q7B, pid = 19460
# ". Lockfile is "D:/youFPGA/Test/Test.sim/sim_1/behav/modelsim/modelsim_lib/msim/xbip_pipe_v3_0_5/_lock".

在文件夹中找到这个文件，然后给他删了

• [Synth 8-3331] design delay__parameterized20 has unconnected port SCLR
• 指出文件中有端口还未连接

# ** Fatal: (vsim-3363) ../../../../Test.srcs/sources_1/new/top_test.v(49): The array length (40) of VHDL port 'm_axis_data_tdata' does not match the width (1) of its Verilog connection (6th connection).
#    Time: 0 ps  Iteration: 0  Instance: /tb_test/inst_top_test/fir_compiler_0_inst File: ../../../../Test.srcs/sources_1/ip/fir_compiler_0/sim/fir_compiler_0.vhd Line: 66

 通常情况下是因代码中设置的端口位数不匹配，或声明有问题

[IP_Flow 19-3664] IP 'mipi_dsi_tx_0' generated file not found 'd:/youFPGA/mipi_tx/mipi_tx.srcs/sources_1/ip/mipi_dsi_tx_0/mipi_dsi_tx_0.dcp'. Please regenerate to continue.

重新生成单个 IP 核

[HDL 9-806] Syntax error near "lite". ["D:/youFPGA/mipi_tx/mipi_tx.srcs/sources_1/new/axi4 lite.v":23]
语法错误