Qemu-STM32(五)：STM32F407加入USART控制器
·
概述
本文主要描述了在Qemu平台中，如何添加STM32F407的USART控制器模拟代码。
板子截图:
参考资料
STM32F4XX TRM手册，手册编号：RM0090
添加步骤
1、在hw/arm/Kconfig文件中添加STM32F4XX_USART，如下所示:
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -338,6 +338,7 @@ config STM32F407_SOC
select OR_IRQ
select STM32F4XX_SYSCFG
select STM32F4XX_EXTI
+ select STM32F4XX_USART2、在include/hw/arm/stm32f407_soc.h文件中添加
--- a/include/hw/arm/stm32f407_soc.h
+++ b/include/hw/arm/stm32f407_soc.h
@@ -25,6 +25,7 @@
#include "hw/arm/armv7m.h"
#include "hw/misc/stm32f4xx_syscfg.h"
#include "hw/misc/stm32f4xx_exti.h"
+#include "hw/char/stm32f4xx_usart.h"
#define TYPE_STM32F407_SOC "stm32f407-soc"
#define STM32F407_SOC(obj) \
@@ -35,6 +36,12 @@
#define EXIT_BASE_ADDRESS 0x40013C00
+#define STM_NUM_USARTS 4
+#define STM32F407_USART1 0x40011000
+#define STM32F407_USART2 0x40004400
+#define STM32F407_USART3 0x40004800
+#define STM32F407_USART6 0x40011400
+
#define FLASH_BASE_ADDRESS 0x8000000
#define FLASH_SIZE 0x100000
#define SRAM_BASE_ADDRESS 0x20000000
@@ -53,6 +60,7 @@ typedef struct STM32F407State {
STM32F4xxSyscfgState syscfg;
STM32F4xxExtiState exti;
+ STM32F4XXUsartState usart[STM_NUM_USARTS];
} STM32F407State;3、在hw/arm/stm32f407_soc.c文件中添加如下代码片段4.在hw/char/Kconfig中添加
--- a/hw/arm/stm32f407_soc.c
+++ b/hw/arm/stm32f407_soc.c
@@ -32,6 +32,15 @@
#include "hw/arm/stm32f407_soc.h"
#include "sysemu/sysemu.h"
+static const uint32_t usart_addr[STM_NUM_USARTS] = {
+ STM32F407_USART1, STM32F407_USART2, STM32F407_USART3,
+ STM32F407_USART6
+};
+
+static const int usart_irq[STM_NUM_USARTS] = {
+ 37, 38, 39, 71
+};
+
static const int exti_irq[] =
{
6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
@@ -42,6 +51,7 @@ static void stm32f407_soc_initfn(Object *obj)
{
STM32F407State *s = STM32F407_SOC(obj);
+ int i;
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
TYPE_ARMV7M);
@@ -49,6 +59,11 @@ static void stm32f407_soc_initfn(Object *obj)
TYPE_STM32F4XX_SYSCFG);
sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
TYPE_STM32F4XX_EXTI);
+
+ for (i = 0; i < STM_NUM_USARTS; i++) {
+ object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F4XX_USART);
+ qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
+ }
}
static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -95,6 +110,19 @@ static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < 16; i++) {
qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
}
+ /* USART controllers */
+ for (i = 0; i < STM_NUM_USARTS; i++) {
+ dev = DEVICE(&(s->usart[i]));
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+ object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+ }
}4.在hw/char/Kconfig中添加
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -38,6 +38,9 @@ config VIRTIO_SERIAL
config STM32F2XX_USART
bool
+config STM32F4XX_USART
+ bool
+
config CMSDK_APB_UART
bool5.在hw/char/Makefile.objs中添加
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -19,6 +19,7 @@ common-obj-$(CONFIG_OMAP) += omap_uart.o
common-obj-$(CONFIG_SH4) += sh_serial.o
common-obj-$(CONFIG_DIGIC) += digic-uart.o
common-obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
+common-obj-$(CONFIG_STM32F4XX_USART) += stm32f4xx_usart.o
common-obj-$(CONFIG_RASPI) += bcm2835_aux.o6.在hw/char/创建新文件stm32f4xx_usart.c
+/*
+ * Copyright (c) 2020 liang yan <yanl1229@163.com>
+ *
+ * STM32F4XX USART Controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/stm32f4xx_usart.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qemu/module.h"
+#include "migration/vmstate.h"
+
+#ifndef STM_USART_ERR_DEBUG
+#define STM_USART_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_USART_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static int stm32f4xx_usart_can_receive(void *opaque)
+{
+ STM32F4XXUsartState *s = opaque;
+
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void stm32f4xx_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ STM32F4XXUsartState *s = opaque;
+
+ s->usart_dr = *buf;
+
+ if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
+ /* USART not enabled - drop the chars */
+ DB_PRINT("Dropping the chars\n");
+ return;
+ }
+
+ s->usart_sr |= USART_SR_RXNE;
+
+ if (s->usart_cr1 & USART_CR1_RXNEIE) {
+ qemu_set_irq(s->irq, 1);
+ }
+
+ DB_PRINT("Receiving: %c\n", s->usart_dr);
+}
+
+static void stm32f4xx_usart_reset(DeviceState *dev)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(dev);
+
+ s->usart_sr = USART_SR_RESET;
+ s->usart_dr = 0x00000000;
+ s->usart_brr = 0x00000000;
+ s->usart_cr1 = 0x00000000;
+ s->usart_cr2 = 0x00000000;
+ s->usart_cr3 = 0x00000000;
+ s->usart_gtpr = 0x00000000;
+
+ qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t stm32f4xx_usart_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F4XXUsartState *s = opaque;
+ uint64_t retvalue;
+
+ DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
+
+ switch (addr) {
+ case USART_SR:
+ retvalue = s->usart_sr;
+ qemu_chr_fe_accept_input(&s->chr);
+ return retvalue;
+ case USART_DR:
+ DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
+ s->usart_sr |= USART_SR_TXE;
+ s->usart_sr &= ~USART_SR_RXNE;
+ qemu_chr_fe_accept_input(&s->chr);
+ qemu_set_irq(s->irq, 0);
+ if (s->usart_cr1 & USART_CR1_M)
+ return s->usart_dr & 0x1FF;
+ else
+ return s->usart_dr & 0xFF;
+ case USART_BRR:
+ return s->usart_brr;
+ case USART_CR1:
+ return s->usart_cr1;
+ case USART_CR2:
+ return s->usart_cr2;
+ case USART_CR3:
+ return s->usart_cr3;
+ case USART_GTPR:
+ return s->usart_gtpr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void stm32f4xx_usart_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F4XXUsartState *s = opaque;
+ uint32_t value = val64;
+ unsigned char ch;
+
+ DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
+
+ switch (addr) {
+ case USART_SR:
+ if (value <= 0x3FF) {
+ s->usart_sr |= value;
+ } else {
+ s->usart_sr &= value;
+ }
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ qemu_set_irq(s->irq, 0);
+ }
+ return;
+ case USART_DR:
+ if (s->usart_cr1 & USART_CR1_M)
+ ch = value & 0x1FF;
+ else
+ ch = value & 0xFF;
+ if (!(s->usart_cr1 & USART_CR1_TE))
+ return;
+ if ((s->usart_sr &USART_SR_TC))
+ s->usart_sr &= ~USART_SR_TC;
+ ch = value;
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
+ s->usart_sr |= USART_SR_TXE;
+ if (s->usart_cr1 & USART_CR1_TXEIE)
+ qemu_set_irq(s->irq, 0);
+ s->usart_sr |= USART_SR_TC;
+ if (s->usart_cr1 & USART_CR1_TCIE)
+ qemu_set_irq(s->irq, 0);
+ break;
+ case USART_BRR:
+ s->usart_brr |= value & 0xFFFF;
+ break;
+ case USART_CR1:
+ if (!(s->usart_cr1 & USART_CR1_TE) && (value & USART_CR1_TE))
+ s->usart_dr = 0xFF;
+ s->usart_cr1 |= value & 0xFFFF;
+ if (s->usart_cr1 & USART_CR1_RXNEIE &&
+ s->usart_sr & USART_SR_RXNE) {
+ qemu_set_irq(s->irq, 0);
+ }
+ break;
+ case USART_CR2:
+ s->usart_cr2 |= value & 0xFFFF;
+ break;
+ case USART_CR3:
+ s->usart_cr3 |= value;
+ break;
+ case USART_GTPR:
+ s->usart_gtpr |= value & 0xFFFF;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ break;
+ }
+}
+
+static const MemoryRegionOps stm32f4xx_usart_ops = {
+ .read = stm32f4xx_usart_read,
+ .write = stm32f4xx_usart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f4xx_usart = {
+ .name = TYPE_STM32F4XX_USART,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(usart_sr, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_dr, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_brr, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_cr1, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_cr2, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_cr3, STM32F4XXUsartState),
+ VMSTATE_UINT32(usart_gtpr, STM32F4XXUsartState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property stm32f4xx_usart_properties[] = {
+ DEFINE_PROP_CHR("chardev", STM32F4XXUsartState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f4xx_usart_init(Object *obj)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_usart_ops, s,
+ TYPE_STM32F4XX_USART, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f4xx_usart_realize(DeviceState *dev, Error **errp)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(dev);
+
+ qemu_chr_fe_set_handlers(&s->chr, stm32f4xx_usart_can_receive,
+ stm32f4xx_usart_receive, NULL, NULL,
+ s, NULL, true);
+}
+
+static void stm32f4xx_usart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f4xx_usart_reset;
+ device_class_set_props(dc, stm32f4xx_usart_properties);
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+ dc->realize = stm32f4xx_usart_realize;
+ dc->vmsd = &vmstate_stm32f4xx_usart;
+}
+
+static const TypeInfo stm32f4xx_usart_info = {
+ .name = TYPE_STM32F4XX_USART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F4XXUsartState),
+ .instance_init = stm32f4xx_usart_init,
+ .class_init = stm32f4xx_usart_class_init,
+};
+
+static void stm32f4xx_usart_register_types(void)
+{
+ type_register_static(&stm32f4xx_usart_info);
+}
+
+type_init(stm32f4xx_usart_register_types)7.在include/hw/char创建stm32f4xx_usart.h文件
+/*
+ * Copyright (c) 2020 liang yan <yanl1229@163.com>
+ *
+ * STM32F4XX USART Controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_STM32F4XX_USART_H
+#define HW_STM32F4XX_USART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define USART_SR 0x00
+#define USART_DR 0x04
+#define USART_BRR 0x08
+#define USART_CR1 0x0C
+#define USART_CR2 0x10
+#define USART_CR3 0x14
+#define USART_GTPR 0x18
+
+#define USART_SR_RESET 0x00C0
+
+#define USART_SR_TXE (1 << 7)
+#define USART_SR_TC (1 << 6)
+#define USART_SR_RXNE (1 << 5)
+
+#define USART_CR1_UE (1 << 13)
+#define USART_CR1_RXNEIE (1 << 5)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_RE (1 << 2)
+#define USART_CR1_M (1 << 12)
+#define USART_CR1_TXEIE (1 << 7)
+#define USART_CR1_TCIE (1 << 6)
+
+#define USART_CR2_CLKEN (1 << 11)
+#define USART_CR2_LINEN (1 << 14)
+
+#define USART_CR3_SCEN (1 << 5)
+#define USART_CR3_HDSEL (1 << 3)
+#define USART_CR3_IREN (1 << 1)
+
+#define TYPE_STM32F4XX_USART "stm32f4xx-usart"
+#define STM32F4XX_USART(obj) \
+ OBJECT_CHECK(STM32F4XXUsartState, (obj), TYPE_STM32F4XX_USART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t usart_sr;
+ uint32_t usart_dr;
+ uint32_t usart_brr;
+ uint32_t usart_cr1;
+ uint32_t usart_cr2;
+ uint32_t usart_cr3;
+ uint32_t usart_gtpr;
+
+ CharBackend chr;
+ qemu_irq irq;
+} STM32F4XXUsartState;
+
+#endif总结
1、本文描述了如何在qemu中添加stm32f407平台上USART控制器实现；
2、完成的提交记录，请查看代码库链接
链接：
1、qemu代码库链接
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