[filemgmt 20-1731] Too many checkpoints files associated with the sub-design 'D:/FPGA/vivado_file/plan C_D30.srcs/sources_1/ip/ddr3_app/ddr3_app.xci'

博主在操作完MIG IP核后重新编译时出现上述报错，解决方法：

在sources中右击MIG IP 核选择Reset Output Products，等此操作运行完成后再右击选择Generate Output Products